Abstract: Personal perspectives on the evolution of CMOS Integrated Circuit processes and tools are provided. The Cost of Ownership metric is discussed for tool development in the context of TSMC’s US fab and their roadmap.  Separately, brief remarks on implantation for material modification for Atomic Layer Etching and solid-state neutron detectors are made.

Bio: Tom Seidel, with a PhD in Physics from Stevens Institute of Technology joined Bell Laboratories in 1965, where he contributed to ion implantation technology. He supervised early CMOS manufacture and received Bell’s ​“Distinguished Member of the Technical Staff” award. Later, at SEMATECH he managed Joint Development and Strategic Technology Programs. Still later at Genus, Inc., he led their Atomic Layer Deposition program. Retiring in 2008, he broadly collaborated, including with Argonne. He has over 100 publications and 28 US patents.