Abstract: FPGAs come with a steep learning curve and the assumption that the user is knowledgeable and trained as a digital ASIC developer. This barrier to entry is being tackled by using two different approaches: 1) high-level synthesis (HLS) where a user programs in a language such as OpenCL and the hardware is automatically generated and 2) overlay processors, where a team of hardware designers build a domain-specific processor on the FPGA and presents it to the user for programming in a domain-specific language for DSP, networking etc.

This talk will discuss the work being done at ESnet and the LBNL Computer Architecture Group on Overlay Processors, drawing on examples from an overlay network processor, as well as an overlay DSP processor. Simple tooling using Python and Jupyter notebooks is all that is assumed on the part of data scientists from ALS and NCEM to interact with the FPGA design team. A cluster with 48 FPGA cards will be made available for all interested users at the Advanced Photon Source to experiment with both HLS and overlays.