Abstract: Negative Capacitor and Ferroelectric Field Effect Transistors (NC-FET, FeFET) promise to sustain Moore’s law and support non-von-Neuman computing architectures by reducing the supply voltage (and thereby, self-heating) below the lowest limit achievable by classical transistors and by making memory elements co-integrated with logic transistors. Conceptually, the reduction in supply voltage is achieved by integrating a negative capacitor in the gate-stack; the internal voltage amplification turns a transistor on and off at voltages much lower than previously presumed possible. Unfortunately, the notion of a ​‘negative capacitor’, the debate regarding experimental demonstrations, apparent disconnect with equations of classical transistors, etc. make NC-FET and FEFET a mysterious and hard-to-understand addition to device literature.

In this talk, I use a simple graphical approach to demystify the device and explain why the experimental results are easy to misinterpret. Since NC-FET and FeFET are special cases of a much broader range of phase-change devices and systems (e.g., transistors, memories, MEMS, logic-in-memory architecture) that operate by tailoring the Landau potential energy landscape, therefore, once these devices are understood, the operation of all other devices would become intuitively obvious as well.

Bio: Muhammad A. is the Jai N. Gupta Professor of Electrical Engineering at Purdue University.