Argonne National Laboratory

Argonne National Laboratory

Pushing computing onto detector silicon

With the availability of advanced microelectronics technology nodes, more digital functionality from the computing domains can be integrated directly into detector silicon to increase data velocity.

Detectors are an integral part in scientific discovery. From Wilhelm Röntgen’s barium platinocyanide screen to Georges Charpak’s multiwire proportional chamber, detectors are what grant scientists the ability to see far beyond human limits. Modern pixel detectors are built on application-specific integrated circuits (ASICs) fabricated at commercial semiconductor foundries. The general trend of making larger and faster detectors is imposing a huge burden on data storage, and more importantly, on data streaming. Thankfully, with the use of more advanced technology, greater digital functionality from the computing domains can be integrated directly into the detector silicon. Among these functionalities, hardware-based streaming compression is finding its way into the modern computing and networking ecosystem.

(Left) Block diagram of pixel detector compression algorithm. FIFO = first in, first out. (Right) Physical layout of the compression in complementary metal-oxide-semiconductor (CMOS) logic. Click image to expand.

Billions of dollars are being spent on next-generation light source facilities in the U.S. and around the world as well as at leadership computing facilities. While the brightness increases with these new accelerator upgrades will be significant, these new sources will not reach their full potential if limited to detectors of the type available today, or those presently seen on the horizon. In addition, scientists have increasingly turned to artificial intelligence (AI) and machine learning (ML) to analyze data. AI/ML-accelerated workflows have been shown not only to be fast enough to keep up with experiments, but also to overcome experimental restrictions of conventional methods.

In this project, we have developed an ASIC digital architecture with on-chip compression for X-ray coherent diffraction imaging at light sources [1-3]. It is lightweight, includes a user-configurable detector, and has frame rates in the 100 kHz to 1 MHz regime.

  1. S. Strempfer, T. Zhou, K. Yoshii, M. Hammer, A. Babu, D. Bycul, J. Weizeorick, M. J. Cherukara, and A. Miceli,   ​“A lightweight, user-configurable detector ASIC digital architecture with on-chip data compression for MHz X-ray coherent diffraction imaging,” Journal of Instrumentation, 17, P10042 (2022).
  2. M. Hammer, K. Yoshii, and A. Miceli, ​“Strategies for on-chip digital data compression for X-ray pixel detectors,” Journal of Instrumentation, 16, P01025 (2021).
  3. M. Hammer, C. Jacobsen, A. Miceli, ​“Digital encoding algorithm for pixelated detectors,” U.S. Patent App. 16/887,706.